Pre-STAC Summit Session, Cadence Workshop

Presummit Sessions are new in Fall 2023 and occur the day before the STAC Summit New York. They include vendor-led sessions that allow for demos, detailed product explanations, round table discussions, etc. They are open for all financial technologists to attend, but space is limited.  Click here for more information.

Cadence provided the following description of their session: 

"HFT systems implement complex packet processing and trading intelligence optimized for speed. With complexity growing and engineering resources becoming harder to find, new techniques to optimize each stage of development are warranted. It’s generally understood that these new techniques require an investment before they yield a return. But what is the extent of the knowledge and resource investment, what can these new techniques deliver, and what is ROI?

This workshop provides answers to those questions. Together with our HFT advisors, we’ve identified 5 key topics and created technical tutorials for each. The workshop features Cadence subject matter experts who will field your questions as we present each of the topics in these mini-tutorials:

• Faster coding and optimization with high-level synthesis led by Dr Amzie Adams, Digital Design Technical Executive
• Get to design confidence faster with comprehensive verification led by Adam Sherer, Verification Technical Executive
• Stand-up cost-effective ASIC development led by Mike Lafferty, Applications Engineering Group Director
• Utilize specialized SerDes IP to reduce latency in HFT SoC led by Jeff Galloway, Principal/Co-Founder/SerDes Architect, Silicon Creations
• Coding SystemVerilog for Simulation Performance led by Adam Sherer, Verification Technical Executive

Eligibility